veriflow-cc — tool profile and history
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
- Language
- Python
- Created
- Last activity
- Topics
- ai-agents
- chip-design
- claude-code-skill
- claude-code-skills
- degital-design
- digital
- eda-automator
- hdl
- iverilog
- llm-agents
- rtl-design
- verilog
- yosys
Current measurement
50GitHub stars+1 (+2.0 %)
measured growthMomentum uses available readings from the last 7 days: measured with at least two comparable readings, estimated otherwise.
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Classifications
- Domains
- Type
- Agents
- Use cases