veriflow-cc
AgentGitHubAktivPython
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
Herkunft der Beschreibung: Originalquelle
Gemessen: 20.10.2026 · 68 Beobachtungen
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https://github.com/bjwanneng/veriflow-ccKlassifikationen
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55Sterne · 20.10.2026
+13 (+31 %)seit 11.08.2026
Genaue Werte · 68 Messungen
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