rtl-skills
OtherGitHubDormantSystemVerilog
Claude Code skills & agents that automate a full RTL/Verilog design flow - architecture, RTL coding, lint, simulation, self-checking testbenches, regression, debug, Vivado synthesis, and docs - driven from a one-page IP spec.
Description provenance: Original source
Measured: Oct 21, 2026 · 69 observations
Domains & Uses
- Domains
- Agents, skills and MCP
- Uses
- Code assistants
Check at the source
Compatibility and prerequisites must be checked in the official documentation.
https://github.com/phamcuong21478/rtl-skillsClassifications
- Nature
- Tool
Measurement history
Comparable readings are grouped by signal and unit.
Stars
18stars · Oct 21, 2026
+2 (+12.5 %)since Oct 15, 2026
Exact values · 7 readings
| Measured | stars | Change |
|---|---|---|
| 18 | 0 | |
| 18 | +1 | |
| 17 | +1 | |
| 16 | 0 | |
| 16 | 0 | |
| 16 | 0 | |
| 16 | · |