rtl-skills

OtherGitHubDormantSystemVerilog

Claude Code skills & agents that automate a full RTL/Verilog design flow - architecture, RTL coding, lint, simulation, self-checking testbenches, regression, debug, Vivado synthesis, and docs - driven from a one-page IP spec.

Description provenance: Original source

Open canonical source

Measured: Oct 21, 2026 · 69 observations

Domains & Uses

Domains: Agents, skills and MCP
Uses: Code assistants

Check at the source

Compatibility and prerequisites must be checked in the official documentation.

https://github.com/phamcuong21478/rtl-skills

Classifications

Nature: Tool

Measurement history

Comparable readings are grouped by signal and unit.

Stars

18stars · Oct 21, 2026

+12 (+200 %)since Aug 11, 2026

Exact values · 69 readings

Measured	stars	Change
Oct 21, 2026	18	0
Oct 20, 2026	18	+1
Oct 19, 2026	17	+1
Oct 18, 2026	16	0
Oct 17, 2026	16	0
Oct 16, 2026	16	0
Oct 15, 2026	16	0
Oct 14, 2026	16	0
Oct 13, 2026	16	0
Oct 12, 2026	16	0
Oct 11, 2026	16	0
Oct 10, 2026	16	0
Oct 9, 2026	16	0
Oct 8, 2026	16	0
Oct 7, 2026	16	0
Oct 6, 2026	16	0
Oct 5, 2026	16	0
Oct 4, 2026	16	0
Oct 3, 2026	16	0
Oct 2, 2026	16	+1
Oct 1, 2026	15	0
Sep 30, 2026	15	0
Sep 29, 2026	15	0
Sep 28, 2026	15	+1
Sep 27, 2026	14	0
Sep 26, 2026	14	0
Sep 25, 2026	14	0
Sep 24, 2026	14	0
Sep 23, 2026	14	0
Sep 22, 2026	14	0
Sep 20, 2026	14	0
Sep 19, 2026	14	0
Sep 18, 2026	14	0
Sep 17, 2026	14	0
Sep 16, 2026	14	0
Sep 15, 2026	14	+1
Sep 14, 2026	13	0
Sep 13, 2026	13	0
Sep 12, 2026	13	+2
Sep 11, 2026	11	0
Sep 10, 2026	11	0
Sep 9, 2026	11	0
Sep 8, 2026	11	0
Sep 7, 2026	11	0
Sep 6, 2026	11	0
Sep 5, 2026	11	+1
Sep 4, 2026	10	0
Sep 2, 2026	10	0
Aug 31, 2026	10	0
Aug 30, 2026	10	0
Aug 29, 2026	10	0
Aug 28, 2026	10	+1
Aug 27, 2026	9	0
Aug 26, 2026	9	+1
Aug 25, 2026	8	0
Aug 24, 2026	8	0
Aug 23, 2026	8	+1
Aug 22, 2026	7	0
Aug 21, 2026	7	0
Aug 20, 2026	7	0
Aug 19, 2026	7	0
Aug 18, 2026	7	0
Aug 17, 2026	7	0
Aug 16, 2026	7	0
Aug 15, 2026	7	0
Aug 14, 2026	7	0
Aug 13, 2026	7	0
Aug 12, 2026	7	+1
Aug 11, 2026	6	·