veriflow-cc
AgentGitHubActivePython
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
Description provenance: Original source
Measured: Oct 20, 2026 · 68 observations
Domains & Uses
- Domains
- Agents, skills and MCP
- Uses
- Workflows
Check at the source
Compatibility and prerequisites must be checked in the official documentation.
https://github.com/bjwanneng/veriflow-ccClassifications
- Nature
- Tool
Measurement history
Comparable readings are grouped by signal and unit.
Stars
55stars · Oct 20, 2026
+1 (+1.9 %)since Oct 14, 2026
Exact values · 7 readings
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| 55 | 0 | |
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| 54 | · |