veriflow-cc

AgentGitHubActivePython

VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

Description provenance: Original source

Open canonical source

Measured: Oct 20, 2026 · 68 observations

Domains & Uses

Domains: Agents, skills and MCP
Uses: Workflows

Check at the source

Compatibility and prerequisites must be checked in the official documentation.

https://github.com/bjwanneng/veriflow-cc

Classifications

Nature: Tool

Measurement history

Comparable readings are grouped by signal and unit.

Stars

55stars · Oct 20, 2026

+4 (+7.8 %)since Sep 22, 2026

Exact values · 29 readings

Measured	stars	Change
Oct 20, 2026	55	0
Oct 19, 2026	55	+1
Oct 18, 2026	54	0
Oct 17, 2026	54	0
Oct 16, 2026	54	0
Oct 15, 2026	54	0
Oct 14, 2026	54	+1
Oct 13, 2026	53	0
Oct 12, 2026	53	+1
Oct 11, 2026	52	0
Oct 10, 2026	52	0
Oct 9, 2026	52	0
Oct 8, 2026	52	0
Oct 7, 2026	52	0
Oct 6, 2026	52	0
Oct 5, 2026	52	0
Oct 4, 2026	52	+1
Oct 3, 2026	51	0
Oct 2, 2026	51	0
Oct 1, 2026	51	-1
Sep 30, 2026	52	0
Sep 29, 2026	52	0
Sep 28, 2026	52	0
Sep 27, 2026	52	0
Sep 26, 2026	52	0
Sep 25, 2026	52	0
Sep 24, 2026	52	+1
Sep 23, 2026	51	0
Sep 22, 2026	51	·