rtl-skills — tool profile and history
Claude Code skills & agents that automate a full RTL/Verilog design flow - architecture, RTL coding, lint, simulation, self-checking testbenches, regression, debug, Vivado synthesis, and docs - driven from a one-page IP spec.
- Language
- SystemVerilog
- License
- Apache-2.0
- Created
- Last activity
- Topics
- chip-design
- claude
- claude-code
- claude-code-skills
- rtl
- rtl-design
- simulation
- systemverilog
- verilog
- verilog-hdl
Current measurement
10GitHub stars+1 (+11.1 %)
measured growthMomentum uses available readings from the last 7 days: measured with at least two comparable readings, estimated otherwise.
Reading history
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Classifications
- Domains
- Type
- Other
- Use cases
Neighbouring tools
These entries declare the same topics. No similarity is inferred: only the shared topics are stated.